Undergraduate Student·Fudan University
Studying memory systems and accelerator design, from architectural models to implementation.
Select the address and copy it. On a touch screen, press and hold.
Tracing served reads to DRAM transfers and examining how measurement windows change dataflow rankings.
An L2 cache observer that preserves simulated cycles, instructions, and output in a three-way trace replay.
My individual ISSCC 2027 Code-a-Chip project, with exact numerical and cycle agreement across 441 model-to-RTL checks.
Selected publication
11th International Conference on Integrated Circuits and Microsystems (ICICM 2026)
Xi’an, China
Best Presentation Award (session)
Recognition
Best Presentation Award (session) · Xi’an, China
East China Regional Second Prize · LoongArch track
Freshman Scholarship
Third Prize · Shanghai, Non-Math A
First Prize · Jiangsu Division
About me
I study Microelectronics Science and Engineering in Fudan University’s Shannon Program. My work focuses on hardware evaluation: how simulators account for memory traffic, how their measurements shape architecture comparisons, and how model predictions compare with RTL.
In the FDUROP Xiyuan Program, I led a three-student study advised by Prof. Keren Zhu (CODA Lab). We examined read-trace consistency in SCALE-Sim and the effect of measurement windows on dataflow rankings. I presented the work at ICICM 2026, where my oral presentation received the Best Presentation Award (session).
I am interested in design automation for AI hardware, especially using system-level models to compare architectural choices and test them against RTL and physical implementations.
Read my full CV (PDF, opens in a new tab)I use Codex extensively to build, test, and refine software.